Power Efficient Sum of Absolute Difference Algorithms for video Compression

Abstract : Video Compression (VC) is one of the resource hungry key element in video communication and is commonly achieved using Motion Estimation (ME). In this paper we proposed power efficient one bit full adder and one of the simple and easy metric called Sum of Absolute Difference (SAD) for estimating the motion vectors in motion estimation. SAD is primarily used to detect motion in the video sub system. Here we proposed power efficient 4X4 and 8X8 SAD architectures. The proposed 4X4 SAD proves that 29%, 63.23% and 61.31% improvement in leakage power, dynamic power and total power respectively as compared with existing 4X4 SAD. Similarly the proposed 8X8 SAD which proves that 57%, 46.16% and 46.78% improvement in Leakage Power (LP), Dynamic Power (DP) and Total Power (TP) respectively as compared with that of existing 8X8 SAD at the gate level. The designs are implemented in ASIC methodology using cadence tools.